The present invention relates to a semiconductor memory device and a method of operating the same. More specifically, the present invention relates to a method of programming a semiconductor memory device.
A semiconductor memory device may include a memory cell array in which data is stored, and the memory cell array may include a plurality of memory cell blocks. Each of the memory cell blocks may include a plurality of cell strings, and each of the cell strings may include a plurality of memory cells.
A program operation of a semiconductor memory device may be performed by selecting one memory cell block out of the plurality of memory cell blocks and on each of pages included in the selected memory cell block. The program operation will be described hereinafter in detail with reference to the accompanying drawings.
FIG. 1 is a circuit diagram of a memory cell block, illustrating a conventional program method.
Referring to FIG. 1, the memory cell block includes a plurality of cell strings STe and STo. The cell strings may be referred to as even strings STe or odd strings STo depending on the order of disposition thereof. Even bit lines BLe are connected to the even strings STe, while odd bit lines BLo are connected to the odd strings STo.
As the integration density of semiconductor memory devices increases, a distance between the even and odd cell strings STe and STo decreases, and a distance between adjacent memory cells also decreases. As a result, interference between the adjacent memory cells increases.
Therefore, in a program method of performing a program operation on the odd strings STe after performing a program operation on the even strings STe, even cells Fe of the even strings STe are programmed to have threshold voltages which are determined to be lower than a target voltage in consideration of interference caused in the even cells Fe during a program of odd cells Fo included in the odd strings STo. Thereafter, the odd strings STo are programmed until threshold voltages of the odd cells Fo reach a target voltage, and then the even strings STe are programmed until threshold voltages of the even cells Fe of the even strings STe reach a target voltage. The above-described program operation is referred to as a pre-program. However, even if the pre-program is applied, interference still occurs due to structural characteristics of adjacent cells and a memory device, which will be described in detail hereinafter.
FIG. 2 is a graph illustrating features of a conventional program method.
Referring to FIG. 2, in a multi-level cell (MLC) programmed in a plurality of program states, a method of programming even cells (refer to Fe of FIG. 1) of a selected page in a first state MPV1 will be exemplarily described.
A pre-program operation may be performed until threshold voltages of the even cells Fe reach a pre-target voltage Vpre lower than a target voltage of the first state MPV1. When all the threshold voltages of the even cells Fe reach the pre-target voltage Vpre (refer to 21), the odd cells (refer to Fo of FIG. 1) may be programmed such that threshold voltages of odd cells Fo reach a target voltage. During a program operation of the odd cells Fo, the threshold voltages of the pre-programmed even cells Fe may increase due to interference (refer to 22). Thereafter, before the threshold voltages 22 of the pre-programmed even cells Fe are finally programmed, it may be determined in which state the pre-programmed even cells Fe are to be programmed by reading data of the pre-programmed even cells Fe. That is, when the threshold voltages of the pre-programmed even cells Fe are lower than a read reference voltage Vtr, the even cells Fe may be programmed to be in the first state MPV1 during a main program operation. When the threshold voltages of the pre-programmed even cells Fe are higher than the read reference voltage Vtr, the even cells Fe may be programmed to be in a second state MPV2 higher than the first state MPV1 during the main program operation.
If the threshold voltages of some of the even cells Fe to be programmed to be in the first state MPV1 excessively increase due to interference and become higher than the reference voltage Vtr (refer to 23), the corresponding memory cells would be programmed to be not in the first state MPV1 but in the second state MPV2 during a main program operation (refer to 24). Accordingly, after the program operation is finished, since data of the corresponding cells is read as the second state MPV2 based on a read voltage Vread, the reliability of the program operation may be degraded. This phenomenon mainly occurs due to interference caused by programming adjacent cells.
Meanwhile, the amount of interference between adjacent cells may vary depending on a structure of a memory device. When a read reference voltage set based on the same interference amount is applied to all semiconductor devices, even if a main program operation is performed after a pre-program operation as described above, reliability may be degraded as described in detail with reference to the following drawings.
FIG. 3 is a cross-sectional view of a conventional memory device.
A cross-section of memory cells included in different cell strings will be described with reference to FIG. 3. A tunnel insulating layer 32 and a floating gate 33 may be stacked on an active region of a semiconductor substrate 31, and an isolation layer 34 may be formed in an isolation region thereof. For example, an upper surface of the isolation layer 34 may be between upper surfaces of the tunnel insulating layer 32 and the floating gate 33. A dielectric layer 35 may be formed along the surfaces of the floating gate 33 and the isolation layer 34, and a control gate 36 serving as a word line may be formed on the dielectric layer 35. Here, each of active regions may become a region in which a cell string is formed.
In particular, an effective height EFH between the upper surface of the isolation layer 34 and a lower surface of the floating gate 33 may greatly affect interference between adjacent cells. For instance, capacitance between the floating gates 33 may vary depending on the effective height EFH, and a depletion region may occur in the control gate 36 due to a program voltage applied to the control gate 36 and voltages applied to channel regions of unselected cell strings and selected cell strings, respectively, during a program operation.
As a result, even if a program operation is performed using the same program voltage, the same program prohibition voltage, and the same program permission voltage, the amount of interference may vary depending on the kind of a semiconductor memory device, thereby degrading the reliability of the program operation.